Advanced packaging technology plays an increasingly important role in the miniaturization of equipment, system integration and performance enhancement. Among many new packaging technologies, sector panel-level packaging (FOPLP) has attracted more interest and has shown the advantages of higher I/O count, integration flexibility, low cost, and small size due to the elimination of substrates . However, FOPLP using epoxy molding compound (EMC) materials faces many technical challenges, such as warping panel processing, difficulty in manufacturing fine-pitch redistribution layers (RDL), and large size due to CTE mismatch between chips and EMC Packaging reliability issues. In addition, for high-performance SIP, advanced FOPLP with multiple layers of fine pitch RDL is required, excellent alignment accuracy, the shortest interconnect wiring between dies, and ultra-small size.


Regarding all the advantages and challenges mentioned above, we have extensive experience with FOPLP on our equipment. At the same time, we have practical applications in South Korea and the United States, so we hope to share this technology with the Chinese semiconductor industry.